The present invention relates to timing errors and in particular but not exclusively to an apparatus and method of handling errors in embedded systems. Adaptive scaling is a technique which places a system as close to a timing failure as possible in order to maximize the energy efficiency of that system. Energy efficiency may be of particular concern for systems with a finite power source such as battery operated systems. In particular but not exclusively, adaptive scaling is useful in embedded systems such as systems on a chip (SoC).
Due to the proximity of an adaptively scaled system to a timing failure, techniques have been proposed for dealing with and detecting timing errors occurring in a system.
Razor is a technique in which a main flip-flop is provided in parallel with a shadow flip-flop. The input data is sampled by the main flip-flop and the shadow flip-flop at different points in time. If an error is detected from the comparison of the output of a shadow latch and the output of the main flip-flop, then the instruction set is replayed. The error may be indicated by the assertion of an error flag. SoC incorporating such techniques need to be designed for instruction replays on the assertion of the error flag.
Modifications have been suggested to Razor in which error detection is provided in a flip flop while correction is performed through architectural replay. In the Razor techniques, instruction replay may be required for every detected error. Each instruction replay consumes power which increases the overall power consumption of a circuit. These techniques may also compromise the throughput of the system on chip SoC.
An additional technique for online timing error resilience has been proposed which masks timing errors by borrowing time from successive pipeline stages. This technique is intrusive and requires specific latches and flip-flops. The existing proposed circuitry has limitations regarding the positioning of an error window and detection of certain kinds of errors.